The present invention relates generally to static memory devices. More particularly, the invention relates to an apparatus and method for reducing the access time after a write operation in a static memory device.
Traditionally, static random access memories (SRAMs) have been designed such that a delay, known as an access time, t.sub.a, must pass before data written in a cell of an SRAM can be read. A typical timing diagram for an SRAM is shown in FIG. 1. In FIG. 1 the falling edge of an internal write pulse 91 is triggered by the falling edge of an external write pulse 93. Similarly, the rising edge of internal write pulse 91 is triggered by the rising edge of external write pulse 93. By using external write pulse 93 to trigger internal write pulse 91, a read access plus recovery time, (t.sub.a +t.sub.R), must pass before the data can be read from a particular memory cell.
The reason that recovery time t.sub.R is present is that the internal write pulse must be given time to allow for changes in data signal 95 to be written in the memory cell. By triggering internal write pulse 91 from the state changes of external write pulse 93, data changes occurring in data signal 95 are detected and written into the memory cell before write cycle, t.sub.wc, ends. The disadvantage of holding the end of internal write signal 91 until the end of external write pulse 93 occurs is that recovery time, t.sub.R, is extended beyond the end of external write cycle, t.sub.wc. The time, t.sub.R, is essentially an access time waiting period which must pass before data in the memory cell can be accessed. Waiting for access of the memory cell slows down any system in which an SRAM employing this prior art design is used. While some SRAM's are specified with t.sub.R =O, this is generally accomplished by setting the access time equal to (t.sub.a +t.sub.R), i.e., a decrease in performance exists but is not explicitly stated on the data sheet.